This invention relates to programmable logic array integrated circuit devices, and more particularly to improving the speed and/or efficiency with which such devices can perform multiplication.
A typical programmable logic device (see, for example, Cliff et al. U.S. Pat. No. 5,909,126, and Cliff et al. U.S. Pat. No. 5,999,015, both of which are hereby incorporated by reference herein) includes a large number of relatively small "modules" of programmable logic and various types of programmably controlled interconnection conductors and other circuit elements for selectively conveying signals to, from, and between the logic modules. Each logic module is programmable to perform any of several relatively small logic tasks. But extremely complex logic can be performed by the device as a whole by interconnecting the logic modules to one another via the interconnection conductors and related circuitry.
In many known programmable logic devices, each logic module can be programmed to perform one place of binary addition on two addend signals and a carry in signal in order to produce a sum out signal and a carry out signal. This is true, for example, of the representative logic module shown in FIG. 2 of above-mentioned U.S. Pat. No. 5,999,015. A frequently occurring elemental operation in binary multiplications, however, involves Adding a multiplicand bit and a multiplier bit to produce one of two addends that are to be added together with a carry in bit to produce a sum out bit and a carry out bit. Because a logic module as described above cannot perform both an AND operation and one place of binary addition, two logic modules are required to perform one elemental multiplication operation of the type mentioned in the immediately preceding sentence.
Some elemental operations in a multiplication are even more complex than those mentioned above. These operations require two separate AND operations on two sets of two multiplicand/multiplier bits. The outputs of the two AND operations are two addend bits that must be added together with a carry in bit to produce sum out and carry out bits. Again, because logic modules of the type described above cannot perform more than one two-input AND or one place of binary addition, three logic modules are required to perform an elemental multiplication operation of the type mentioned in the three immediately preceding sentences.
It will be seen from the foregoing that multiplications tend to require large numbers of logic modules on a programmable logic device. And because many of the elemental multiplication operations involved require two or even three logic modules which must be interconnected via interconnection conductors and related circuitry, multiplications tend to be slowed down by the need to pass signals through the interconnection conductors as part of most of the elemental operations, as well as between elemental operations.
In view of the foregoing, it is an object of this invention to provide improved programmable logic device circuitry for performing multiplication.
It is a more particular object of this invention to reduce the number of logic modules on a programmable logic device that are required to perform multiplication.
It is another more particular object of this invention to provide programmable logic circuitry which can perform multiplication more rapidly.